Gated Clocks

The Bluespec compiler (BSC) performs checks as it compiles the code.  BSC's safety checks around clocks are about making sure that the clock connected to a module meets the requirements of that module.  These requirements are specified in two places: 
  1. Imported modules: it's in the import-BVI; 
  2. Synthesized BSV modules: it is determined by attributes on the module. If the default behavior for synthesized modules is too strict, you might need to add attributes to your modules.


If an imported Verilog module cannot support a gated clock, then the import looks like this:

(A)   input_clock  clk(CLK);

However, if an imported Verilog module *can* support a gated clock, there are still two possibilities: 
  1.  the module requires access to the gate signal (via a port)
  2.  the gate signal is not relevant to operation of the module.

The first case is expressed like this:

(B)   input_clock  clk(CLK, CLK_GATE);

The second case is expressed like this:

(C)   input_clock  clk(CLK, (*unused*)CLK_GATE);

This statement (C) is saying that the module doesn't have a port for the gate signal, but it's not because the module can't be connected to a gated clock, only that the module doesn't need access to the gate for proper behavior.

When BSC connects a clock to an input of type (A), it reports an error if the clock has an associated gate signal -- only ungated clocks are allowed.  When BSC connects a clock to inputs of type (B) or (C), there is never an error, because both gated and ungated clocks can be connected.  (If an ungated clock is connected, the gate port is tied to True.)

The other side, then, is how clocks are declared -- telling BSC whether they have a gate or not.

In an import-BVI, this is simple.  It either has a gate or it doesn't:

(D)   output_clock gen_clk(CLK_OUT);

(E)   output_clock gen_clk(CLK_OUT, CLK_OUT_GATE);

Synthesized modules

Input clocks to synthesized modules are ungated by default.  If you want your module to support gated clock inputs, then you need to use an attribute such as: gate_all_clocks, gate_input_clocks, etc.

Output clocks of synthesized modules are always gated.  Unfortunately, BSC doesn't yet support attributes to specify otherwise.

So here's where a problem can arise.  If you import a Verilog module that has an ungated output clock, and you pass this up through the hierarchy of your design -- as an output clock of the parent module -- then the clock will become a gated clock, and BSC will no longer allow you to connect it to modules that require ungated clocks.

Error Message

The following error message may be displayed if the clock gate specifications don't match.

Error: "design.bsv", line 68, column 20: (G0063)
 The module `MODULE' expects the input clock `clk' to be ungated, but in the
 instantiation `mod' it has been connected to a clock whose gate is not
 constant True.