A module consists of three things: state, rules that operate on that state, and the module's interface to the outside world (surrounding hierarchy). A module definition specifies a scheme that can be instantiated multiple times.
The state conceptually consists of all state in the sub-hierarchy headed by this module; ultimately, it consists of all the lower leaf module instances. Rules are the fundamental means to express behavior in Bluespec SystemVerilog. Interfaces consist of methods that encapsulate the possible transactions that clients can perform, i.e., the micro-protocols with which clients interact with the module. When compiled into RTL, an interface becomes a collection of wires.
A module definition begins with a module header, followed by zero or more module statements, ending with the closing endmodule keyword. The module header contains the keyword module, the module name, parameters, arguments, interface type and provisos. The module name on the closing endmodule statement is optional. See the BSV Reference Manual for the complete module definition syntax.
module name (parameters)(Interface_type interface_name) provisos;
One difference between SystemVerilog and Verilog is that SystemVerilog separates the declaration of an interface from the module definition. This allows you to define a common interface once, and use that interface in multiple modules, without having to repeat the interface definition in each of the implementation modules.
As shown above, the module definition includes the interface being provided by the module.
When defining the module, specify the provided interface type in the module header:
module mkM (BusInterface); //BusInterface is a previously defined Interface type
When instantiating (using) the module, instantiate the interface:
In order to generate code for a Bluespec SystemVerilog design (for either Verilog or Bluesim), it is necessary to indicate to the compiler which module(s) are to be synthesized. A module that is marked for code generation is said to be a synthesized module.
In order to be synthesizable, a module must meet the following characteristics:
As mentioned above, a module is synthesizable if its interface is convertible to wires.
To be convertible to bits, a type must be in the Bits typeclass.
For a module to be synthesizable its additional parameters must be of type Clock, Reset, or a type convertible to bits. For example, if a parameter is a datatype, such as Integer, which is not in the Bits typeclass, then the module cannot be separately synthesized.
A module can be marked for synthesis in one of two ways.
(* synthesize *)
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