Value methods outputs data from a module.  In the simplified FIFO example:

interface FIFO;
     method  Action                 enq(Bit#(32) data);
     method  Bit#(32)               first();
     method  ActionValue#(Bit#(32)) deq() ;
endinterface 

The second method is a value method. It only outputs data from the module. In this case, we are return a 32 bit bus, which the Bluespec compiler names the same as the method name, first. The generated Verilog for the method named first is:

   //method Bit#(32) first();
   output        RDY_first;
   output [31:0] first; 

Notice that this value method reads the data from the FIFO and drives it out on a bus named first. Bluespec automatically generates a RDY_first signal which is driven with notEmpty. The compiler can then use this RDY signal to allow the data to be used and read. The default name of the ready signal generated is RDY_methodname. The default name can be overridden using compiler attributes.

Implicit Signals

Bluespec automatically provides appropriate handshaking signals and logic for each method of an interface.

There is no EN in this case, but one might be generated if it was needed.