//
// Generated by Bluespec Compiler, version 2007.03 (build 10564, 2007-03-30)
// 
// On Tue Jul 17 14:20:09 EDT 2007
// 
// Method conflict info:
// Method: start
// Sequenced after: result
// Conflicts: start
//  
// Method: result
// Conflict-free: result
// Sequenced before: start
//  
// 
// Ports:
// Name                         I/O  size props
// RDY_start                      O     1
// result                         O    32 reg
// RDY_result                     O     1
// CLK                            I     1 clock
// RST_N                          I     1 reset
// start_x                        I    32
// start_y                        I    32
// EN_start                       I     1
// 
// No combinational paths from inputs to outputs
// 
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif

module mkMult1(CLK,
	       RST_N,
	       start_x,
	       start_y,
	       EN_start,
	       RDY_start,
 	       result,
	       RDY_result);
  input  CLK;
  input  RST_N;
  
  // action method start
  input  [31 : 0] start_x;
  input  [31 : 0] start_y;
  input  EN_start;
  output RDY_start;
  
  // value method result
  output [31 : 0] result;
  output RDY_result;

  // signals for module outputs
  wire [31 : 0] result;
  wire RDY_result, RDY_start;

  // register d
  reg [31 : 0] d;
  wire [31 : 0] d$D_IN;
  wire d$EN;

  // register product
  reg [31 : 0] product;
  wire [31 : 0] product$D_IN;
  wire product$EN;

  // register r
  reg [31 : 0] r;
  wire [31 : 0] r$D_IN;
  wire r$EN;

  // inputs to muxes for submodule ports
  wire [31 : 0] MUX_d$write_1__VAL_2,
		MUX_product$write_1__VAL_1,
		MUX_r$write_1__VAL_2;

  // remaining internal signals
  wire [30 : 0] r_BITS_31_TO_1__q1;

  // action method start
  assign RDY_start = r == 32'd0 ;

  // value method result
  assign result = product ;
  assign RDY_result = r == 32'd0 ;

  // inputs to muxes for submodule ports
  assign MUX_d$write_1__VAL_2 = { d[30:0], 1'd0 } ;
  assign MUX_product$write_1__VAL_1 = product + d ;
  assign MUX_r$write_1__VAL_2 =
	     { r_BITS_31_TO_1__q1[30], r_BITS_31_TO_1__q1 } ;

  // register d
  assign d$D_IN = EN_start ? start_x : MUX_d$write_1__VAL_2 ;
  assign d$EN = EN_start || r != 32'd0 ;

  // register product
  assign product$D_IN =
	     ((r & 32'd1) != 32'd0) ? MUX_product$write_1__VAL_1 : 32'd0 ;
  assign product$EN = (r & 32'd1) != 32'd0 || EN_start ;

  // register r
  assign r$D_IN = EN_start ? start_y : MUX_r$write_1__VAL_2 ;
  assign r$EN = EN_start || r != 32'd0 ;

  // remaining internal signals
  assign r_BITS_31_TO_1__q1 = r[31:1] ;

  // handling of inlined registers
  
  [email protected](posedge CLK)
  begin
    if (!RST_N)
      begin
        d <= `BSV_ASSIGNMENT_DELAY 32'd0;
	product <= `BSV_ASSIGNMENT_DELAY 32'd0;
	r <= `BSV_ASSIGNMENT_DELAY 32'd0;
      end
    else
      begin
        if (d$EN) d <= `BSV_ASSIGNMENT_DELAY d$D_IN;
	if (product$EN) product <= `BSV_ASSIGNMENT_DELAY product$D_IN;
	if (r$EN) r <= `BSV_ASSIGNMENT_DELAY r$D_IN;
      end
  end
   
  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    d = 32'hAAAAAAAA;
    product = 32'hAAAAAAAA;
    r = 32'hAAAAAAAA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on
endmodule  // mkMult1