The first order determiners of power are typically architecture and micro-architecture. With limited or no ability to make changes, when you're designing at the RTL level, the scope of optimizations are limited to just finding local minima. Rapid, safe architectural changes enable a much wider scope of architectures to be explored for a more optimal solution. Bluespec makes it possible to make rapid, safe architectural changes in order to find the global power, area, timing and latency minimums.
As SoCs continue to become larger and faster, gated clocks and multiple clock domains are increasingly used to manage power, to support multiple, varied communication interfaces, and to re-use older IP, that can demand different clock requirements. Interconnection among these different clock domains has become difficult to manage and prone to error, as most commercially available verification tools do not guarantee correct implementation to handle metastability. As a result, synchronization issues are sometimes not discovered until the chip is manufactured into silicon – adding significant delays and costs to the design of the chip. In addition, implementing and managing control logic around clock gating for power management is burdensome and contributes to design errors.
Bluespec has added integrated clock management and formal clock connectivity verification to enhance its multiple clock domain (MCD) support. Bluespec's toolset automates gated-clock implementations for power management by automatically identifying and managing interface communications between active and inactive clock domains. By incorporating clocking into its semantic model, Bluespec's toolset simplifies complex clock topology implementations and ensures that mis-connections are caught at the time of synthesis.