Advanced data structures, such as vectors, lists, and structures, are difficult to view during simulation and debugging since they are converted into bits during compilation. You can use the Probe package which is provided in the Bluespec library, to ensure that signals of interest are not optimized away by the compiler and are given a known name. The Probe primitive is used just like a register, except that only a write method exists. Since reads are not available, a Probe does not impact scheduling.
The first step is to define a specialized probe module based on the module mkProbe provided in the BSV library. In this example we'll call our module mkS_Probe. This module instantiates a mkProbe module for each field of the structure and defines the write method to include each field of the structure.
The specialized module, mkS_Probe, has to be kept in sync with the structure definition. For each field added to the structure, two lines must be added to the mkS_Probe module definition; one for the instantiation and one for the write. A unique module must be written for each unique data structure, but they all use the same basic techniques.
// Probe library is needed for this technique
Once we've defined the mkS_Probe module, we can use it to view the signals in the structure. The remainder of this code shows an example of using mkProbe and mkS_Probe.
// Define an interface and module for the example.
After compiling, the generated Verilog will contain signals named <instance_name>$PROBE, however no actual Probe instance will be created. The only side effects of a BSV Probe instantiation relate to the naming and retention of the associated signal in the generated Verilog.
In the generated Verilog code, the following code segment will be found:
The first line corresponds to the rprobe, and the is assigned the current value of r[11:0]. The structure information is not present. The next 3 lines show therprobe_current instance of mkS_Probe module, while the last 3 lines show the rprobe_new instance. Note that within each of these instances the specific structure fields are presented, which will aid in the observation of the design. For net-list synthesis, these signals will be removed, since they are not connected to further down-stream logic.