Communication between methods and rules occur through module level constructs such as registers, FIFOs, or other modules. When a rule needs to access data from an interface, the input (action) method can write the data to a register, and the rule can read the value in the next clock cycle. (Note: A configuration register can be used to avoid schedule blocking when writing registers in methods and reading them in rules)

To avoid this extra register and the associated cycle latency, Bluespec provides the RWire package. Conceptually, RWire is a 0-delay wire with an appropriate interface. The interface allows one write per cycle, and the write must occur before the read.

Shared Address Bus

This example shows the use of an RWire, via the mkWire module to share information between separate interface methods. This example uses a shared address bus example.

interface Memory_ifc ;
        method  Action   addr( Addr_t addrin ) ;
        method  Action   read ( ) ;
        method  Data_t   read_value() ; 
        method  Action   write ( Data_t datain ) ;
endinterface

(* synthesize *)
module mkTest3 ( Memory_ifc );

   // Creates a Reg interface, but it is really a zero-latency wire.
   Reg#(Addr_t) addrbus <- mkWire ;
  
   Reg#(Maybe#(Data_t))  data_out <- mkReg (Invalid) ;
    
   method Action addr( addrin ) ; 
       addrbus <= addrin ;
   endmethod
   
   method Action read();
     $display( "calling read with address: %h", addrbus );
   endmethod
 
   method Action write( data ); 
      $display( "calling write with address: %h -- data:", addrbus, data );
   endmethod
  
  method read_value() if ( data_out matches tagged Valid .d );
     read_value = d  ;
  endmethod