|To aid in design debug, there are several bsc techniques which can be used, either alone or in combination.
There are several compiler flags which may be helpful in debugging BSV designs. For example, the -keep-fires option will preserve the CAN_FIRE_<rule> and the WILL_FIRE_<rule> signals in the generated Verilog, even if they can be optimized away.
By adding (* synthesize *) directive on modules, the Bluespec generated Verilog will have more levels of hierarchy, which may allow easier debug. Note that the scheduling phase of Bluespec may produce a different, typically less optimized, scheduler than one where the entire design is scheduled. Hence these synthesis directives should be removed before gate-level synthesis. Note that the synthesis directive can only be used on non-polymorphic modules.
Functions can also be synthesized as a Verilog module, by preceding the function with a (* noinline *) attribute. Like the (* synthesize *) directive the generated Verilog may be less efficient when using this attribute, since optimizations cannot take place across these boundaries. Parameterized functions cannot be synthesized directly into Verilog.
Yet another technique is to add a "monitor signal" or Probe primitive. The Probe primitives are not optimized nor removed in Bluespec, so the signal will remain for debug. For example,
Note that these types of monitors can only be added in a module context, that is not in functions, and can only be assigned in action contexts, such as rules, or action methods.
Probes can also be used to view complex data structures.