One means to control a simulation is to instantiate a counter at the top level, and key actions and possibly values from the counter values. In the example below, we setup a 16 bit counter, which is then used to start the VCD dumping, rule init, end the simulation rule stop, and control some action, rule action1. There is one additional rule, which constantly increments the count -- rule count.
// parameterized module -- a common module for testing all dut
Notice that this example also uses a module parameter of type interface Pusher. That is this module uses another interface as its parameter.
This can be invoked as shown below.
(* synthesize *)
The top-level interface is "Empty", that is, it contains only a clock and reset line in the synthesized version. For modules with "Empty" interfaces, Bluespec provides a test driver module, one which applies a reset, and then drives the clock indefinitely. The module is located in $BLUESPECDIR/Verilog/main.v and can be invoked by vcs using the following command-line:
vcs $BLUESPECDIR/Verilog/main.v +define+TOP=tst_fifo +libext+.v -y $BLUESPECDIR/Verilog/ *.v