Learning Bluespec

Learning Bluespec

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Advanced Bluespec

Rules

  • Rules Of Rules - more detail on exactly how rules work
  • Rules of Wires - more detail on wires and how they work in BSV
  • Are rule guards always mutually exclusive?

Using Advanced Types

  • Using Structures
  • Using the Maybe type
  • Using Vectors

System Design Examples

  • Synchronous State Machine
  • Using RWire to Avoid Registers and Latency

Testbenches

  • Controlling Simulation
  • Stored Test Patterns
  • Generating Random Test Patterns

Helping the Scheduler

  • Rules vs. Always Blocks
  • Alleviating Read/Write Conflicts with ConfigReg
  • Register Updates

Debugging Bluespec Designs

  • Debugging Hints and Tips
  • Debugging Long Compilations
  • Viewing Complex Data Structures

Clocks

  • Multi Clock Designs  pos and neg edge (and pos reset) in bsv, and DDR...
  • Working with Gated Clocks

Import BVI  You may want or need to use an existing verilog block inside BSV... 

Power  Strategies for using Bluespec to reduce power consumption


Subpages (17): Configuration Register Controlling Simulation Debugging Hints and Tips Debugging Long Compilations Generating Random Test Patterns Import BVI Multi Clock Designs Mutually Exclusive Rules Power Register Updates Rules Of Rules Rules Of Wires Rules vs. Always Blocks Stored Test Patterns Synchronous State Machine Using RWire Viewing Complex Data Structures
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