In Verilog, combinational logic can be described by either continuous assignments, or with always blocks. RTL synthesis tools transform these structures into a logic function, which are then mapped to gates. In Bluespec, combinational logic is best described by functions. Moreover, Bluespec compilation has the power to automatically generate control logic for Finite State Machines (FSMs) and handshake logic between FSMs or interface methods.
Verilog continuous assignments can be thought of as functions, and combinational logic cones as a composition of functions. This conceptual model maps directly onto Bluespec, which encourages the use of functions. The significant difference between continuous assigns with and without functions is that functions can be defined once and instantiated many times, whereas continuous assigns explicitly have one instantiation in hardware.
During Verilog synthesis both combinational and sequential
always blocks are transformed from its sequential execution
(imperative) semantic to a functional semantic for easy synthesis into
logic gates. That is, sequential if-then-else statements are
transformed to muxes, with both branches evaluated in parallel. With
Bluespec, the model is to divide the program into functions, using the
many paradigms available in Bluespec.
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