The attribute reset_by= allows the user to assert which reset an input port is associated with, to specify that the port has no_reset, or to associate the port with the default_reset. If the reset_by= attribute is not provided, the default reset will be used.
Attribute Syntax
module modulename (... (*reset_by="resetname" *) argument...) ;
The reset_by = attribute immediately precedes the input port the reset is associated with.
To specify that a port is not reset by any reset or by the default reset, the term no_reset is specified for the reset string.
Example
(* reset_by = "no_reset" *) argument (* reset_by = "default_reset" *) argument
BSV Example
module mkMod (Clock c2, Reset r2, (* reset_by = "r2" *) Bool b, ModIfc ifc);
Generated Verilog
module mkMod(CLK_c2, RST_N_r2, b, CLK, RST_N); input CLK_c2; input RST_N_r2; input b; input CLK; input RST_N;
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