The attribute clocked_by= allows the user to assert which clock an input port is associated with, to specify that the port has no_clock, or to associate the clock with the default_clock. If the clocked_by= attribute is not provided, the default clock will be used.
Attribute Syntax
module modulename (... (*clocked_by="clockname" *) argument...) ;
The clocked_by = attribute immediately precedes the input port the clock is associated with.
To specify that a port is not clocked by any clock or by the default clock, the appropriate term is used for the clock string.
Example
(* clocked_by = "no_clock" *) argument (* clocked_by = "default_clock" *) argument
BSV Example
module mkMod (Clock c2, (* clocked_by = "c2" *) Bool b, ModIfc ifc);
Generated Verilog
module mkMod(CLK_c2, b, CLK, RST_N); input CLK_c2; input b; input CLK; input RST_N;
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