The port protocol attributes always_enabled and always_ready remove unnecessary ports. In all cases the compiler verifies that the attributes are correctly applied and generates an error if they are not.

The attribute always_enabled specifies that no enable signal will be generated for the associated interface methods. The methods will be executed on every clock cycle and the compiler verifies that the caller does this.

The attribute always_ready specifies that no ready signals will be generated. The compiler verifies that the associated interface methods are permanently ready. always_enabled implies always_ready.

Attribute Syntax

(* always_enabled, always_ready *)
(* always_enabled = string, always_ready = string)

where string is the name of the method or subinterface the attribute is modifying. As with all attributes, they can be in a single statement, separated by a comma, or in separate statements.

The always_ready and always_enabled attributes can be associated with the method declarations, sub-interface declarations, or the interface declaration itself.

The attributes are applied when the interface is implemented within a module, not at the declaration of the interface.

BSV Example

interface IfcCabinCntrl#(type floors, type direction);
  method Action      destinationFloor(floors a);
  method Action      nearFloor;
  method direction   motorCntrl;
endinterface

// the attribute is on the module, not the method defintion
(* synthesize,  always_enabled = "motorCntrl", always_ready = "motorCntrl" *)
module mkCabinCntrl (IfcCabinCntrl#(Floors, Direction));
   ...
endmodule

Generated Verilog

 // action method destinationFloor
 input  [3 : 0] destinationFloor_a;
 input  EN_destinationFloor;
 output RDY_destinationFloor;

 // action method nearFloor
 input  EN_nearFloor;
 output RDY_nearFloor;

 // value method motorCntrl
 output [1 : 0] motorCntrl;