The synthesize attribute marks a module for code generation and directs the compiler to generate instantiations of the module as separate module definitions during code generation. Not all BSV modules can be synthesized modules. A module is synthesizable if its interface is a type whose methods and subinterfaces are all convertible to wires. An interface must be fully specified, i.e. all parameters in polymorphic interfaces must be fully defined at compile time. In the example below, size_t must be defined at compile time in order for the module to be synthesizable.

Example:

(* synthesize *)
module mkCounter (IfcCounter#(Bit#(size_t));
   ...
endmodule

While it is recommended that modules be marked for synthesis in the BSV code, using the synthesize attribute, a module can also be marked for code generation during compilation by using the -g compiler flag on the command line. The name of the module to be synthesized must be provided after the flag. If, in the above example, the module mkCounter is in the file Counter.bsv, to generate Verilog the command would be:

bsc -verilog -g mkCounter Counter.bsv