When a module is synthesized, one oscillator port is created for each clock input (including the default clock). The gate for the clock is defaulted to a logical 1. The attributes gate_all_clocks and gate_input_clocks= specify that a second clock port be generated for the gate.
The attribute gate_all_clocks will add a gate port to the default clock and to all input clocks. The attribute gate_input_clocks= is used to individually specify each input clock which should have a gate supplied by the parent module.
Note that when there is a gate port the compiler can no longer
assume the gate is always logical 1. This can cause an error if the
clock is connected to a submodule which requires the gate to be logical
(* gate_all_clocks *)
(* synthesize, gate_all_clocks *)
The gate_input_clocks= attribute can be used to add a gate port to the default clock.
(* synthesize, gate_input_clocks = "default_clock" *)