When a module is synthesized, one oscillator port is created for each clock input (including the default clock). The gate for the clock is defaulted to a logical 1. The attributes gate_all_clocks and gate_input_clocks= specify that a second clock port be generated for the gate.

The attribute gate_all_clocks will add a gate port to the default clock and to all input clocks. The attribute gate_input_clocks= is used to individually specify each input clock which should have a gate supplied by the parent module.

Note that when there is a gate port the compiler can no longer assume the gate is always logical 1. This can cause an error if the clock is connected to a submodule which requires the gate to be logical 1.

Attribute Syntax

(* gate_all_clocks *)
(* gate_input_clocks = "inputclockname" *)

BSV Example 1: gate_all_clocks

(* synthesize,  gate_all_clocks *)
module mkMod(Clock clk2, Reset reset1, ModIfc ifc);

Generated Verilog 1

module mkMod(CLK_clk2,
             CLK_GATE_clk2,
             RST_N_reset1,
             CLK,
             CLK_GATE,
             RST_N);
  input  CLK_clk2;
  input  CLK_GATE_clk2;
  input  RST_N_reset1;
  input  CLK;
  input  CLK_GATE;
  input  RST_N;
   

The gate_input_clocks= attribute can be used to add a gate port to the default clock.

BSV Example 2: gate_input_clocks

(* synthesize, gate_input_clocks = "default_clock"  *)
module mkMod(Clock clk2, Reset reset1, ModIfc ifc);

Generated Verilog 2

module mkMod(CLK_clk2,
             RST_N_reset1,
             CLK,
             CLK_GATE,
             RST_N);
  input  CLK_clk2;
  input  RST_N_reset1;
  input  CLK;
  input  CLK_GATE;
  input  RST_N;