The attributes default_clock_osc=, default_clock_gate= and default_reset=
provide the names for the default clock, default gate and default reset
ports for a module. When a name for the default clock or reset is
provided, any prefix attribute for that port is ignored.
Default Naming
default clock = CLK default gate = CLK_GATE default reset = RST_N
Attribute Syntax
(* default_clock_osc = "defaultclockname" *) (* default_clock_gate = "defaultgatename" *) (* default_reset = "defaultresetname *)
BSV Example 1: default
(* synthesize, default_clock_osc = "CLOCK", default_reset = "RESET", default_clock_gate = "default_gate_unused" *) module mkMod(Clock clk2, Reset reset1, ModIfc ifc);
Generated Verilog 1
module mkMod(CLK_clk2, RST_N_reset1, CLOCK, default_gate_unused, RESET); input CLK_clk2; input RST_N_reset1; input CLOCK; input default_gate_unused; input RESET;
The attributes no_default_clock and no_default_reset are used to remove the ports for the default clock and the default reset.
BSV Example 2: no default
(* synthesize, default_clock_osc = "no_default_clock", default_reset = "no_default_reset" *) module mkMod(Clock clk2, Reset reset1, ModIfc ifc);
Generated Verilog 2
module mkMod(CLK_clk2, RST_N_reset1, no_default_clock, no_default_reset); input CLK_clk2; input RST_N_reset1; input no_default_clock; input no_default_reset;
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