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Clock and Reset Prefix Naming Attributes

The generated port renaming attributes clock_prefix=, gate_prefix=, and reset_prefix= rename the ports for the clocks, clock gates and resets respectively, in a module by specifying a prefix string to be added to each port name. The prefix is used only when a either a default name or argument-level name is not provided for the port. Without a provided name, the port name is created from the prefix and the argument name.

These attributes are associated with a module and are only applied when the synthesize attribute is specified for the module.

The default clock, reset and gate will be named just using the prefix names.

Default Naming

clock_prefix = CLK
clock name = CLK_argumentname
default clock = CLK
gate_prefix= CLK_GATE
gate name = CLK_GATE_argumentname
default gate = CLK_GATE
reset_prefix= RST_N
reset name = RST_N_argumentname
default reset = RST_N

Attribute Syntax

(* clock_prefix = "clockprefixname", gate_prefix = "gateprefixname", 
reset_prefix = "resetprefixname" *)
module definition

The attributes can also be put on separate lines

(* clock_prefix = "clockprefixname" *)
(* gate_prefix = "gateprefixname" *)
(* reset_prefix = "resetprefixname" *)
module definition

BSV Example 1

(* synthesize, clock_prefix = "CK" *)
module mkMod(Clock clk2, ModIfc ifc);

Generated Verilog 1

module mkMod(CK_clk2,
input CK_clk2;
input CK;
input RST_N;

Where CK is the default clock (using the user-supplied prefix), RST_N is the default reset (using the default prefix), and CK_clk2 is the oscillator for the input clk2 (using the user-supplied prefix).

If a prefix is specified as the empty string, then no prefix will be used when creating the port names; that is the argument name alone will be used as the name. In this case a name must be provided for the default.

BSV Example 2

(* synthesize, clock_prefix = "CK", reset_prefix = "", 
default_reset = "RST" *)
module mkMod(Clock clk2, Reset reset1, ModIfc ifc);

Generated Verilog 2

module mkMod(CK_clk2,
input CK_clk2;
input reset1;
input CK;
input RST;