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Clock and Reset Naming Attributes

The non-default clock and reset inputs to a module will have a port name created using the argument name and any associated prefix for that port type. This name can be overridden on a per-argument basis by supplying argument-level attributes that specify the name for the port.

Default Naming

clock name = clockprefix_argumentname
gate name = gateprefix_argumentname
reset name = reset_prefix_argumentname

Attribute Syntax

(* osc = "clockname" *)
(* gate = "gatename" *) 
(* gate = gate_inhigh *) or (* gate = gate_unused *)
(* reset= "resetname" *)

As with all attributes, multiple attributes can be combined on a single line, separated by commas, or put on multiple lines. The attribute is positioned immediately before the object it is modifying.

BSV Example

(* synthesize, gate_all_clocks, default_gate_unused *)
module mkMod((* osc="ACLK", gate="AGATE" *) Clock clk, 
             (* reset="RESET" *) Reset rst, 
             ModIfc ifc);

Generated Verilog

module mkMod(ACLK,
             AGATE,
             RESET,
             CLK,
             RST_N);
  input  ACLK;
  input  AGATE;
  input  RESET;
  input  CLK;
  input  RST_N;

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